1. Technical Field
The present disclosure relates to a layout of a semiconductor device, and more particularly to a semiconductor device capable of achieving increased speed and increased degree of integration.
2. Description of the Related Art
According to a conventional semiconductor device, a transistor is formed in each of an N-type well region and a P-type well region that are formed so as to extend in a horizontal direction, and the N-type well regions and the P-type well regions are alternately arranged in a vertical direction. The above structure is known as a standard cell structure in general.
According to the conventional standard cell structure (see, for example, Unexamined Japanese Patent Publication No. 2008-300765), a power supply is supplied to the transistor in each unit cell, through a power supply wiring extending in the vertical direction and a power supply wiring extending in the horizontal direction. That is, according to the conventional standard cell structure, a potential is supplied to a substrate of the cell, through two metal wiring layers that are also used for to a signal wiring. Thus, the conventional standard cell structure has severe design restrictions on arrangement of the signal wiring.
According to the conventional standard cell structure (see, for example, Unexamined Japanese Patent Publication No. 2002-334933), a specific cell (hereinafter, referred to as the tap cell) is separately prepared to supply a substrate power supply to cells in a cell row, and the power supply is supplied from the specific cell to a substrate (well region) of the transistor.